Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version1846317
date_generatedWed Aug 9 10:14:14 2017 os_platformWIN64
product_versionVivado v2017.1 (64-bit) project_ide8e3ea7cc26f4485aaf6ad9097d40b07
project_iteration8 random_id1c4eae36b7e55381bdb2c3ddf82a827d
registration_id211066216_1777517862_0_160 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-6500U CPU @ 2.50GHz cpu_speed2592 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram7.000 GB total_processors1

vivado_usage
gui_resources
abstractcombinedpanel_add_element=1 abstractcombinedpanel_remove_selected_elements=3 abstractfileview_reload=2 addsrcwizard_specify_simulation_specific_hdl_files=1
basedialog_cancel=15 basedialog_ok=47 basedialog_yes=6 clockcreationpanel_add_this_clock_to_existing_clock=2
clockcreationpanel_clock_name=2 clockcreationpanel_enter_positive_number=1 clockcreationpanel_specify_fall_edge_time_of_clock=1 cmdmsgdialog_ok=7
constraintschooserpanel_create_file=2 createconstraintsfilepanel_file_name=8 createsrcfiledialog_file_name=8 definemodulesdialog_define_modules_and_specify_io_ports=29
definemodulesdialog_entity_name=7 editiodelaytablepanel_edit_io_delay_table=23 filesetpanel_file_set_panel_tree=26 filesetpanel_messages=1
flownavigatortreepanel_flow_navigator_tree=44 getobjectsdialog_enumerate=2 getobjectsdialog_find=8 getobjectspanel_set=4
gettingstartedview_create_new_project=1 hduallist_find_results=8 hduallist_move_all_items_to_right=1 hduallist_move_selected_items_to_left=1
hduallist_move_selected_items_to_right=7 hduallist_selected_names=1 iodelaycreationpanel_delay_value=2 iodelaycreationpanel_delay_value_specifies=1
iodelaycreationpanel_specify_clock_pin_or_port=5 iodelaycreationpanel_specify_clock_pin_or_port_to_which_output=1 iodelaycreationpanel_specify_list_of_ports=3 mainmenumgr_edit=6
mainmenumgr_file=22 mainmenumgr_flow=4 mainmenumgr_help=4 mainmenumgr_open_recent_file=7
mainmenumgr_tools=3 mainmenumgr_unselect_type=1 mainmenumgr_view=11 mainmenumgr_window=2
mainwinmenumgr_layout=12 msgtreepanel_message_view_tree=2 navigabletimingreporttab_timing_report_navigation_tree=2 pacommandnames_auto_connect_target=7
pacommandnames_auto_update_hier=1 pacommandnames_close_design=1 pacommandnames_close_project=2 pacommandnames_create_timing_constraint=2
pacommandnames_goto_netlist_design=1 pacommandnames_open_hardware_manager=2 pacommandnames_run_bitgen=1 pacommandnames_save_design=1
pacommandnames_simulation_live_run=5 pacommandnames_simulation_live_run_all=1 pacommandnames_simulation_relaunch=2 pacommandnames_simulation_run_behavioral=2
pacommandnames_xdc_create_clock=2 pacommandnames_xdc_set_input_delay=1 pacommandnames_xdc_set_output_delay=1 pacommandnames_zoom_in=1
partchooser_boards=1 paviews_code=1 programdebugtab_open_target=11 programdebugtab_program_device=8
programfpgadialog_program=7 programfpgadialog_specify_bitstream_file=1 progressdialog_cancel=1 projectnamechooser_create_project_subdirectory=2
projectnamechooser_project_name=1 rdicommands_delete=1 rdicommands_redo=1 rdicommands_undo=1
rdiviews_waveform_viewer=28 sdcgetobjectspanel_specify_clock_source_objects=2 signaltreepanel_signal_tree_table=40 simulationobjectspanel_simulation_objects_tree_table=6
srcchooserpanel_add_or_create_source_file=3 srcchooserpanel_add_sources_from_subdirectories=1 srcchooserpanel_create_file=6 srcchoosertable_src_chooser_table=5
srcmenu_ip_hierarchy=1 syntheticagettingstartedview_recent_projects=1 waveformnametree_waveform_name_tree=4 xdccategorytree_xdc_category_tree=22
xdceditorpanel_create_assertion_constraint=2 xdceditorpanel_create_clock_constraint=1 xdceditorpanel_create_exception_constraint=2 xdceditorpanel_create_input_constraint=1
xdceditorpanel_create_other_constraint=1 xdceditorpanel_create_output_constraint=1 xdceditorview_apply_all_changes_to_xdc_constraints=3
java_command_handlers
addsources=3 autoconnecttarget=6 closedesign=1 closeproject=2
editdelete=1 editredo=1 editundo=1 launchprogramfpga=8
newproject=1 openhardwaremanager=3 openrecenttarget=2 reporttimingsummary=2
runbitgen=10 runimplementation=1 runsynthesis=4 savedesign=4
showview=7 simulationrelaunch=2 simulationrun=2 simulationrunall=1
simulationrunfortime=5 viewtaskimplementation=1 viewtasksynthesis=2 xdccreateclock=3
xdcsetinputdelay=2 xdcsetoutputdelay=4 zoomin=8
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=6 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=1 carry4=7 fdre=44 gnd=1
ibuf=1 lut1=28 lut3=1 lut4=1
lut5=3 lut6=1 obuf=16 vcc=1
pre_unisim_transformation
bufg=1 carry4=7 fdre=44 gnd=1
ibuf=1 lut1=28 lut3=1 lut4=1
lut5=3 lut6=1 obuf=16 vcc=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
timing-16=16 xdch-2=16

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.001822 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=High
confidence_level_overall=Medium customer=TBD customer_class=TBD devstatic=0.071726
die=xc7a35tcpg236-1 dsp_output_toggle=12.500000 dynamic=0.011959 effective_thetaja=5.0
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.009745 input_toggle=12.500000 junction_temp=25.4 (C)
logic=0.000051 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.083685
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=cpg236
pct_clock_constrained=1.000000 pct_inputs_defined=100 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000340 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=7.5 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=5.0 user_junc_temp=25.4 (C)
user_thetajb=7.5 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000354 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.012616
vccaux_total_current=0.012970 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000162
vccbram_total_current=0.000162 vccbram_voltage=1.000000 vccint_dynamic_current=0.002294 vccint_static_current=0.009555
vccint_total_current=0.011849 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.002736 vcco33_static_current=0.001000
vcco33_total_current=0.003736 vcco33_voltage=3.300000 version=2017.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=7
fdre_functional_category=Flop & Latch fdre_used=44 ibuf_functional_category=IO ibuf_used=1
lut1_functional_category=LUT lut1_used=1 lut3_functional_category=LUT lut3_used=1
lut4_functional_category=LUT lut4_used=1 lut5_functional_category=LUT lut5_used=3
lut6_functional_category=LUT lut6_used=1 obuf_functional_category=IO obuf_used=16
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=7 lut_as_logic_util_percentage=0.03
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=44 register_as_flip_flop_util_percentage=0.11
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=7 slice_luts_util_percentage=0.03
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=44 slice_registers_util_percentage=0.11
fully_used_lut_ff_pairs_fixed=0.11 fully_used_lut_ff_pairs_used=0 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=7 lut_as_logic_util_percentage=0.03
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=1
lut_ff_pairs_with_one_unused_lut_output_fixed=1 lut_ff_pairs_with_one_unused_lut_output_used=1 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=1 lut_flip_flop_pairs_util_percentage=<0.01 slice_available=8150 slice_fixed=0
slice_used=27 slice_util_percentage=0.33 slicel_fixed=0 slicel_used=25
slicem_fixed=0 slicem_used=2 unique_control_sets_used=2 using_o5_and_o6_fixed=2
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=7
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=214850 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=2
dsp=0 effort=2 estimated_expansions=166158 ff=44
global_clocks=1 high_fanout_nets=0 iob=17 lut=7
movable_instances=78 nets=106 pins=420 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tcpg236-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=flowing_led -verilog_define=default::[not_specified]
usage
elapsed=00:00:27s hls_ip=0 memory_gain=426.930MB memory_peak=661.586MB

xsim
command_line_options
-sim_mode=behavioral -sim_type=default::